The invention relates to a method of forming semiconductor device isolation trenches and, more particularly, to a method of forming trenches having on the walls thereof a high integrity silicon dioxide insulator.
In the integrated circuit (IC) technology it is usually necessary to isolate various active and passive devices in the IC. The preferred isolation is dielectric isolation because it allows butting of the circuit elements against the isolation and thereby result in greater density of packing of the active and passive devices on the IC chip. The art is replete with a variety of dielectric isolation schemes. Within the dielectric isolation arena, dielectric-filled trench isolation has received particular attention because of its ability to meet the basic requirements of an interdevice isolation of being efficient in electrical isolation and space utilization while maintaining good surface planarity. The overall process sequence of trench isolation fabrication consists of four basic process steps: (1) trench formation; (2) trench filling; (3) surface planarization; and (4) excess material removal. In this context, U.S. Pat. No. 3,966,577 to Hochberg discloses a sputter etching method to achieve dielectric isolation using grown or deposited silicon dioxide to fill etched trenches.
IBM Technical Disclosure Bulletin, Vol. 21 (1), page 144, June 1977 by S. A. Abbas entitled "Recessed Oxide Isolation Process" describes a reactive ion etching (RIE) method to make recessed silicon dioxide filled trenches by partially filling the trenches with evaporated polysilicon material and then oxidizing the material.
U.S. Pat. No. 4,104,086 to Bondur et al and assigned to the present assignee (which, incidentally, contains extensive citation of prior isolation techniques) teaches a method of achieving well-filled deep narrow grooves with near vertical walls by employing RIE. The method consists of the formation of slightly tapered narrow trenches cut through buried highly doped silicon regions, thermal oxidation of the trenches and proper filling-in of the remaining trenches with a vapor deposited dielectric material. This patent emphasizes the need for for forming slightly tapered walls and then addresses the dependency of the quality and planarity of the dielectric filling material on the trench taper angle and trench width. This patent also employs a back etching (by RIE) of the filling material which covers the total wafer to remove the material everywhere from the surface to leave only the isolation pockets.
U.S. Pat. No. 4,139,442 to Bondur et al and assigned to the present assignee teaches a method of simultaneously making both shallow and deep recessed oxide isolation trenches. Shallow and deep trenches of equal narrow width are formed in the silicon substrate by RIE followed by thermally oxidizing the vertical trench walls to completely fill the trenches.
U.S. Pat No. 4,222,792 to Lever et al and assigned to the present assignee discloses a method of forming a deep wide dieletric-filled isolation trench. In this method a wide trench is formed in the surface of a silicon substrate, a thin oxide layer is formed on the trench walls by thermal oxidation of the trench and a layer of organic glass resin in a solvent is spin coated over the surface of the substrate and within the trench. The resin glass within the trench is exposed to an electron beam to render the glass within the trench impervious to a developing solvent. The remainder of the resin glass is stripped away by developing in a solvent, and the resin glass plug within the trench is converted to silicon dioxide by heating in an oxygen ambient. Finally, a layer of silicon dioxide is deposited over the entire surface of the substrate and etched away to planarize the trench.
IBM Technical Disclosure Bulletin Vol. 21 (4) pages 1466-1467, September 1978 entitled "Method of Etching/Filling Deep Trench Isolation for Large-Scale Integrated Devices" by Logan et al discloses use of magnesium oxide as a combination of etch mask and lift-off mask during oxide-filled trench fabrication. A trench is formed in a silicon substrate by RIE using MgO layer having a trench pattern. An oxide is grown on the exposed surfaces of the trench. The trench is filled by sputter depositing SiO.sub.2 to a depth less than the trench depth. The oxide sputtered in the device areas is removed by lift-off by dissolving the MgO layer.
U.S. Pat. No. 4,238,278 to Antipov and assigned to the present assignee discloses forming deep and shallow trenches in a silicon substrate. Deep trenches are formed by RIE in the substrate. The trenches are partially filled with oxide by a combination of thermal oxidation of the trench surfaces and chemical vapor deposition (CVD). Filling of deep trenches is completed by the deposition of polysilicon to the surface level of the CVD oxide. Shallow trenches are then etched in the substrate and the exposed silicon and polysilicon corresponding to the shallow and deep trenches, respectively, is thermally oxidized.
U.S. Pat. No. 4,356,211 to Riseman and assigned to the present assignee describes a method of forming air-dielectric isolation regions in silicon. Trenches are formed in the silicon substrate by RIE after having etched openings in an oxide-nitride dual layer on the substrate surface. The surfaces of the trenches are oxidized prior to depositing polycrystalline silicon on the trench sidewalls and on the walls defining the openings in the dual layer. By selectively doping the portion of the polysilicon on the walls of the openings in the dual layer so that this polysilicon will oxidize at a faster rate than the polysilicon on the trench walls, thermal oxidation causes the polysilicon to close in the upper end of each of the trenches while leaving an air space therebeneath to form the dielectric isolation regions.
U.S. Pat. No. 4,544,576 to Chu et al and assigned to the present assignee discloses deep glass-filled trench isolation. After forming trenches in a silicon substrate by RIE, an oxide trench liner is grown. A glass having a coefficient of thermal expansion closely matching that of the substrate is deposited to entirely or partially fill the trench. The structure is then fired until the glass particles fuse into a continuous glass layer and final smoothing if necessary is accomplished.
U.S. Pat. No. 4,571,819 to Rogers et al describes a method of forming oxide-filled trenches without leaving a void or insufficiently filled trench in the center of the trench. In this method, silicon dioxide trench fill containing 3-9 weight percent of N or P type dopant material is reflowed at 950.degree.-1150.degree. C. to collapse any voids therein and produce surface planarity. An underlaying oxide-polysilicon-nitride layer permits the formation and reflow of the doped oxide and remains in place in the trench.
U.S. Pat. No. 4,509,249 describes a method of fabricating polysilicon-filled trench isolation. After forming a U-shaped groove in a silicon substrate by RIE and thermally oxidizing the trench surfaces to form a thick oxide, undoped polysilicon is deposited to fill the groove. The polysilicon material which is deposited on the substrate surface is etched off while simultaneously recessing the polysilicon in the groove followed by completion of groove filling with bias sputtered oxide.
With the advent of the very large scale integrated circuit and its requirement (due to low dopant concentrations in the substrate material) of establishing electrical contact to the substrate containing the IC at the top side rather than back side thereof for reverse biasing the substrate, filling of trenches with conductive material came into vogue. Doped polysilicon has been favored as the conductive trench fill because it gives rise to minimal crystallographic defect formation during the various subsequent thermal cycles owing to the excellent thermal expansion coefficient compatibility of the polysilicon with the silicon material. In this context IBM Technical Disclosure Bulletin, Vol. 25 (2) pages 588-589, July 1982 by Antipov et al entitled "Post Emitter Polysilicon Trench Isolation" teaches use of doped polysilicon as the trench filling material. After forming all the elements of a bipolar device on a silicon substrate, using an oxide-nitride etch mask, a deep trench is formed in the substrate by RIE. The trench surfaces are oxidized to form a thin oxide layer, followed by deposition of a thin nitride layer. The oxide-nitride layers at the bottom of the trench are removed followed by deposition of doped polysilicon to fill the trench and establish substrate contact via the trench bottom. Excess polysilicon is removed followed by oxidation to convert the top portion of the polysilicon trench fill into a passivation layer.
IBM Technical Disclosure Bulletin, Vol. 25 (5), pages 2288-2291 by Anantha et al entitled "Method of Forming Polysilicon-Filled Regions in an Integrated Circuit Device" discloses a variation of the Antipov et al method where in the trench walls are coated with a CVD oxide and polysilicon trench fill material is recessed substantially below the substrate surface.
U.S. Pat. No. 4,256,514 to Pogge and assigned to the present assignee discloses a process of forming in a silicon substrate deep and shallow oxide-filled trenches in conjunction with polysilicon-filled trenches, the latter for establishing electrical contact with the substrate from the top surface of the substrate. A CVD oxide layer formed on the walls of the polysilicon-filled trenches to provide the necessary dielectric isolation between devices IC.
In the trench isolation technology it is important that the trench liner and the trench-fill material be of high quality and integrity. Particularly in polysilicon-filled trench technology, since interdevice isolation is provided by the insulator layer (invariably, a thick oxide) on the sidewalls of the trench, while the doped polysilicon fill serves as the electrically conductive medium for biasing the substrate, it is imperative that the trench sidewall be of high integrity. However, the prior art methods of forming the trench sidewall oxide insulator, regardless of whether formed by CVD or thermal oxidation have basic shortcomings.
To elaborate on the above shortcomings, reference is made to FIG. 1 wherein is shown a deep trench coated with a CVD oxide. Numeral 10 designates a silicon substrate in which the trench is formed and 12 and 14 designate thin oxide and nitride trench liners, respectively. The CVD oxide sidewall is designated by 16 and the polysilicon fill, which is of the same conductivity type as the substrate 10, by 18. The CVD oxide sidewall insulator 16, although provides excellent conformality desired of trench sidewall, suffers from susceptibility to erosion 20 at the top thereof during the wet (e.g., buffered hydrofluoric acid) etching steps associated with the excess material (invariably, a thermally grown oxide mask) removal step of trench fabrication mentioned hereinabove or with subsequent device fabrication. This erosion of the CVD oxide sidewall 16 occurs because the etch rate of CVD oxide is extremely high (typically, 5-6 times) compared to that of thermally grown oxide. As a result of this erosion, subsequent utilization of the substrate 10 leads to serious electrical shorting problems. For example, in state-of-the-art bipolar device fabrication wherein polysilicon base is defined such that it overlaps the trench, the doped polysilicon base material will fill the narrow grooves 22 forming conductive polysilicon rails embedded therein. This leads to base-to-isolation shorts and leakage through the doped polysilicon rails.
In addition to the vertical erosion during wet etching, the CVD sidewall oxide 16 is also susceptible to lateral erosion. Since the etch rate of the CVD oxide is inherently high, the various etching steps to remove the nitride 14 and oxide 12 from the trench bottom and trench cleaning steps prior to filling with polysilicon 18 tend to thin down the CVD sidewall oxide 16 as indicated by numeral 24 in FIG. 1. Since the thickness of the sidewall insulator 16 is key to the capacitance associated with the trench (the thinner the insulator, the larger is the capacitance), thinning of the sidewall oxide 16 leads to unacceptable trench sidewall capacitance.
One way of minimizing the lateral erosion 24 (FIG. 1) and preserving the trench CVD sidewall oxide thickness is by providing protective layers. However, this adds to the complexity and cost of the trench fabrication process. Likewise, the erosion 20 at the top can be minimized by means of additional barrier layers (such as silicon nitride or sacrificial undoped polysilicon), but at the expense of additional cost and process complexity.
Turning to the shortcomings of the second prior art method of forming the sidewall oxide, viz., by thermal oxidation of the silicon trench, in this method, which involves covering the silicon substrate with an oxidation resistant trench-definition mask, RIE of the trench and a high temperature thermal oxidation of the trench surfaces, the grown oxide is sensitive to the dopant type and concentration variations in the substrate. For example, referring to FIGS. 2A and 2B, wherein the substrate 30 is P type, contains a blanket N+ subcollector layer 32 of a high dopant concentration and an N type epitaxial silicon layer 34 of a lower dopant concentration than the N+ layer 32, uniform oxidation will not take place at the trench sidewalls. Referring to FIG. 2A, due to the higher dopant concentration in the subcollector layer 32, the trench portion corresponding to the layer 32 will undergo enhanced oxidation leading to a distortion 36 of the original trench wall profile. Subsequent etching step to remove the oxide at the trench bottom to facilitate substrate contacting, leads to pinholes, discontinuities and other defects in the oxide sidewall due to localized thinning thereof. Consequently, upon filling the trench with highly (P) doped polysilicon, the P dopant will outdiffuse into the substrate via the pinhole and other defects in the grown sidewall oxide causing the pinch-off defects 40. A similar pinch-off defect 42 will occur, as illustrated in FIG. 2B, at the top of the trench near the interface between the epitaxial layer 34 and the trench-definition mask (not shown) due to thinning of sidewall oxide 44 at the top corners of the trench during the etch steps to remove the oxide 44 at the trench bottom and the trench-definition mask. The pinch-off defects 40 and 42 result in a low isolation breakdown.
The invention solves these and other problems by a novel process which is simple and straight-forward.
It is an object of the invention to provide a high integrity oxide sidewall for trench isolation to alleviate the low trench isolation breakdown characteristic of the prior art.
It is another object of the invention to provide a trench sidewall oxide which exhibits the conformality of a CVD oxide and the etch resistance of thermally grown oxide.
As used herein the phrase "polysilicon oxide" means oxide obtained by a complete thermal oxidation of polysilicon.